Video Interface Registers
Last Updated Sept. 19th, 2003
By: Azimer
3.3. Video Interface
3.3.1. Introduction
3.3.2. Timing Registers
3.3.3. FrameBuffer Registers
3.3.4. Scaling Registers
3.3.5. Anti-Aliasing Registers
The primary focus of the VI is to display the external frame buffers rendered by the graphics processor to the TV screen. The VI consists of TV Timing Registers, FrameBuffer Registers, Scaling Registers, and Anti-Aliasing. External Frame Buffers (XFB) are allocated in System RAM, and can utilized double of triple frame buffering through vertical sync interruptions. The Graphics Processor writes to its own Embedded Frame Buffer (EFB) and writes to the XFB using hardware. Not much is done with VI Registers once everything is configured and no VI-specific effects are necessary.
Not much is known at the moment about the timing registers.
To be completed soon
To be completed soon
3.3.5. Anti-Aliasing Registers
To be completed soon
To be completed...